1. Field of the Invention
This invention relates to a memory circuit, or more in particular to a semiconductor memory circuit including a PNPN construction and being small in power consumption.
2. Description of the Prior Art
The construction of a semiconductor memory circuit is available in two types. One is a symmetric circuit such as a flip-flop circuit which consumes power in "on" and "off" states or "1" and "0" states; and the other is an asymmetric circuit which consumes no power in "off" state taking advantage of the self-holding ability of the PNPN construction. The former has excellent characteristics of high stability and responsiveness in operation and finds many applications. One of the advantages of the latter, on the other hand, is small power consumption and is effectively utilized in the fields where low power consumption is imperative, thus making possible a highly efficient memory. The memory circuit used as a holding circuit for the speech path switch in the telephone exchange, for example, is most frequently held in "off" state and therefore its low power consumption is almost vital.
A well-known asymmetric memory circuit with PNPN construction is shown in FIG. 1. In this drawing, reference numeral 1 designates a memory cell, numeral 2 a selective input section and numeral 3 a selective read-out section. This circuit operates in accordance with the truth table of FIG. 2. The circuit of FIG. 1 has the excellent feature that neither the memory cell 1 of PNPN construction including the transistors Q.sub.1 and Q.sub.2 nor the selective input section 2 including the transistor Q.sub.3 consumes power when the memory circuit is held "off". In this circuit configuration, however, the writing operation of the memory cell 1 is performed directly by selecting the memory cell 1 according to the inputs X and Y. In reading the "on" or "off" state in which the memory cell 1 is held, it is necessary to use a selector circuit 3 other than the selective input section 2. Provision of separate selector circuits with individual input terminals for writing and reading operations is uneconomical in view of an increased number of terminals required for integrated circuit construction as well as an increased number of controlled gates in the stage preceding to the selector circuits and complicated control operation. The increased number of controlled gates in the preceding stage consumes more electric power and therefore is undesirable.